1. Field of the Invention
The present invention generally relates to the formation of high performance transistors with reduced short channel effects at small size on wafers or chips of silicon-on-insulator (SOI) construction.
2. Description of the Prior Art
The potential for increased performance and functionality of integrated circuits by increased proximity of devices has provided a strong incentive to increase integration density to decrease length of signal propagation paths, and increase the number of devices which can be formed on a single chip of a given size. Reduction of signal path length reduces interconnection resistance and capacitance and allows reduction of signal propagation time as well as susceptibility to capacitive or inductive coupling of noise. Such reductions in interconnect capacitance must also be accompanied by reductions in device dimensions both to reduce parasitic capacitances which reduce switching speed and to allow optimal reduction of interconnect length consistent with suitable dimensions for isolation structures. Accordingly, lithographic techniques have become very sophisticated and can produce minimum feature sizes of a fraction of a micron.
In general, while semiconductor processing techniques have been developed to form structures having dimensions much smaller than can be resolved by lithographic exposure techniques, at least one lithographic exposure is necessary to define the location and general dimensions of a device or other structure. However, while some structures can be formed at such small sizes, others cannot and adjustments in operating parameters are often required. In other cases, difficulty in scaling semiconductor structures when seeking to exploit newly developed lithographic capabilities may be the principal limiting factor in the successful reduction of active device dimensions or limit the performance which can be obtained from an active device of a given size at the limit of lithographic resolution. Some active device structures simply do not scale well to smaller sizes.
For example, in field effect transistors, short channel effects which cause leakage and reduction in resistance differential between xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d states have been recognized for many years as the conduction channel length was reduced in transistor designs. This problem led to the development of lightly doped drain structures, now more generally referred to as extension implants since optimal impurity concentrations can be substantial while the dimensions thereof are generally very small. Also, gate to substrate capacitance has limited performance and led to so-called xe2x80x9chaloxe2x80x9d implants to increase the impurity concentration gradient in the substrate below the gate structure. Both of these structures require that the impurity concentration be well-controlled and the concentration gradients be very steep, particularly in devices of small size.
In general, impurities are placed in desired locations by implantation which can be controlled to sub-lithographic dimensions by known techniques. However, implantation must be followed by a closely controlled heat treatment or annealing process to repair lattice damage from the implantation and to activate the impurity by incorporation in the lattice structure. Such heat treatment also causes diffusion of the impurity which cannot be avoided and the implant location must often be adjusted to compensate for the diffusion so that the final impurity location will be as intended. The location of impurities and the multi-dimensional geometry of impurity concentration gradients prior to annealing is particularly critical in extremely small devices.
The mechanics of diffusion are inherent material properties and are well-understood to depend upon the materials (and the microstructure thereof), temperature, time and impurity concentration gradient. Many state-of-the-art semiconductor structure designs therefore have a heat budget which cannot be exceeded without compromise of the intended electrical properties of the device.
Viewed another way, a given amount of heat treatment required following impurity implantation to repair lattice damage and activate the impurity will inevitably lead to a reduction in the steepness of impurity concentration gradient while decreased size of active semiconductor devices, and field effect transistors, in particular, makes the steepness of impurity concentration gradients much more critical in smaller devices in order to obtain optimal device performance. This can be understood from the fact that a scaling of a transistor to smaller dimensions would require increase in the impurity concentration gradient while that increase in concentration gradient may not be possible or available consistent with annealing after an impurity implantation and other device impurity concentration requirements.
To obtain high performance and consistency of conduction characteristics of transistors formed on a chip or wafer, silicon-on-insulator substrates have been employed in recent years, largely due to the extremely high quality of monocrystalline silicon which is produced in a relatively thin surface layer. However, certain electrical characteristics and device structure designs may be complicated by the placement of the high quality surface layer on an insulator which insulates it from the bulk or handling substrate provided to reduce fragility of the wafer or chip. In particular, deep structures, contacts and buried elements such dual gate transistor designs that may provide significant performance enhancements may be difficult to form and process windows may be significantly restricted.
At the same time, however, many semiconductor manufacturing processes are very mature and well-developed and, possibly, having tool costs largely amortized. Therefore, there is substantial incentive to develop device designs which can be fabricated at extremely small size on SOI substrates without major departures from established and well-understood processes or, to the extent such major departures may be necessary, to develop device designs which can be fabricated using alternative by nevertheless mature and well-understood processes. However, most such designs, to date, when scaled to extremely small sizes remain subject to a significant degree of short channel effects and/or require new processes which may be expensive and of uncertain manufacturing yield. In general, reduction of short channel effects has not been optimal due to the physical constraints and difficulties in developing steep impurity profile gradients regardless of the processes attempted.
By the same token, when seeking to obtain maximal performance of devices approaching the limits of lithographic resolution, current density in all parts of the device becomes of substantial importance. While substantial improvements have been made within active regions of transistors, most improvement in contact design have focused on materials to reduce bulk resistance and metal adhesion. However, it has recently been fount that conventional contact geometries cannot be directly applied to some technologies or present problems of high current density at some locations within them that are significant to overall device performance. For example, raised source and drain (RSD) structures must be formed when field effect transistors are formed on very thin SOI in order to provide sufficient volume of silicon to develop silicide contacts (and for other reasons) but these structures and other xe2x80x9cflatxe2x80x9d structures formed substantially parallel to the substrate surface necessarily have geometries which cannot avoid concentration of current at some location within them. At the present time, there have been few, if any, alternatives to flat source/drain contacts due to the need to lithographically define the implant regions.
It is therefore an object of the present invention to provide a field effect transistor design which can be fabricated on SOI wafers or chips at extremely small size including sub-lithographic channel lengths and extremely high integration density with well-understood and mature processes.
It is another object of the invention to provide a transistor having improved source/drain contact geometry at extremely small sizes and which do not concentrate current density.
It is a further object of the invention to provide a transistor design suitable for extremely high density integration which allows increased precision of location of implanted impurities and precision of geometry of impurity concentration gradients.
It is another object of the invention to provide a manufacturing method which can be carried out with high manufacturing yield to form high performance transistors with much reduced susceptibility to short channel effects.
In order to accomplish these and other objects of the invention, a method of fabricating a transistor is provided including steps of forming a polysilicon seed in contact with a conduction channel of a transistor, and epitaxially growing a polysilicon source/drain contact region from the polysilicon seed and/or implanting impurities in a polysilicon seed formed adjacent a conduction channel of a transistor, and difflusing the impurities into the conduction channel.
In accordance with another aspect of the invention a semiconductor device is provided comprising a polysilicon seed formed adjacent to a conduction channel of a transistor, and a polysilicon source/drain region epitaxially grown from said polysilicon seed to form a contact.